@Bill's Notes 21st October 2026 app.a .syntax unified; .cpu cortex-m33; .thumb .include "C:/5e5/STM32H5E5.inc" .section .text; .word RAM1_POST; .word init + 1 .global init; init: @prime tx fifo before clocking ldr r0,=SPI1_BASE; ldr r1,=0x5a5a5a5a str r1,[r0,#SPI1_TXDR]; str r1,[r0,#SPI1_TXDR]; str r1,[r0,#SPI1_TXDR]; str r1,[r0,#SPI1_TXDR] @wait for SPI rx fifo full (RXP) next_trans: ldr r0,=SPI1_BASE; wait1: ldr r2,[r0,#SPI1_SR]; tst r2,#(1<<0); beq wait1 ldr r4,[r0,#SPI1_RXDR]; ldr r5,[r0,#SPI1_RXDR]; ldr r6,[r0,#SPI1_RXDR]; ldr r7,[r0,#SPI1_RXDR] @read spi1 rx str r7,[r0,#SPI1_TXDR]; str r5,[r0,#SPI1_TXDR]; str r6,[r0,#SPI1_TXDR]; str r4,[r0,#SPI1_TXDR] @reverse spi1 tx @dispatch transaction using token method ldr r0,=token_base; ldr r1,=token_end token_loop: ldmia r0!,{r2,r3}; cmp r2,r4; beq match; cmp r0,r1; blo token_loop; b next_trans; match: bx r3 @wait for SPI tx empty (TXP) and rx fifo full (RXP) ram_load: ldr r0,=SPI1_BASE; wait2: ldr r2,[r0,#SPI1_SR]; tst r2,#(1<<1); beq wait2 @test TXP str r4,[r0,#SPI1_TXDR]; str r5,[r0,#SPI1_TXDR]; str r6,[r0,#SPI1_TXDR]; str r7,[r0,#SPI1_TXDR] @prime tx fifo wait3: ldr r2,[r0,#SPI1_SR]; tst r2,#(1<<0); beq wait3 @test RXP @store four words in ram (r5 holds ram base address r6 holds the ram end address) ldr r2,[r0,#SPI1_RXDR]; str r2,[r5]; add r5,r5,#0x04; ldr r2,[r0,#SPI1_RXDR]; str r2,[r5]; add r5,r5,#0x04 ldr r2,[r0,#SPI1_RXDR]; str r2,[r5]; add r5,r5,#0x04; ldr r2,[r0,#SPI1_RXDR]; str r2,[r5]; add r5,r5,#0x04 ldr r7,[r0,#SPI1_SR]; cmp r5,r6; blo ram_load; b next_trans @put SPI1_SR into r7 for spi1 tx (status info) @branch to the app loaded to ram ram_run: ldr sp,[r5]; ldr r1,[r5, #0x04]; bx r1 spi1_test: b next_trans .align 4; token_base: .word 0x91578dd4,spi1_test+1 .word 0x3d28e804,ram_load+1 .word 0x607f096d,ram_run+1 .word 0xa54c9b21,next_trans+1 .word 0xd1e45abd,next_trans+1 .word 0x3df3dce0,next_trans+1 .word 0x9caf78bd,next_trans+1 .word 0x47e3a33b,next_trans+1 .word 0x7a5318c2,next_trans+1 .word 0x7f820d3b,next_trans+1 token_end: .ltorg; .org 0x10000